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general description the max14595 is a dual-channel, bidirectional logic- level translator designed specifically for low power consumption making it suitable for portable and battery- powered equipment. externally applied voltages, v cc and v l , set the logic levels on either side of the device. a logic signal present on the v l side of the device appears as the same logic signal on the v cc side of the device, and vice-versa. the device is optimized for the i 2 c bus as well as the management data input/output (mdio) bus where often high-speed, open-drain operation is required. when ts is high, the device allows the pullup to be connected to the i/o port that has the power. this allows continuous i 2 c operation on the powered side without any disruption while the level translation function is off. the part is specified over the extended -40 n c to +85 n c temperature range, and is available in 8-bump wlp and 8-pin tdfn packages. applications portable and battery-powered electronics devices with i 2 c communication devices with mdio communication general logic-level translation benefits and features s meets industry standards ? i 2 c requirements for standard, fast, and high* speeds ? mdio open drain above 4mhz* s allows greater design flexibility ? down to 0.9v operation on v l side ? supports above 8mhz push-pull operation s ultra-low power consumption ? 7 a v cc supply current ? 3 a v l supply current s provides high level of integration ? pullup resistor enabled with one side power supply when ts is high ? 12k i (max) internal pullup ? low transmission gate r on : 17 i (max) s saves space ? 8-bump, 0.4mm pitch, 0.8mm x 1.6mm wlp package ? 8-pin, 2mm x 2mm tdfn package typical operating circuit 19-6170; rev 0; 12/11 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max14595.related . *requires external pullups. v l = +1.2v v l * v l * v cc * v cc * v cc = +3.0v * pullups are optional for high-speed, open-drain operation. 0.1f +1.2v system controller +3v system gnd gnd gnd en ts v l v cc iovl1 sda slk iovl2 iovcc2 iovcc1 sda slk 1f max14595 max14595 low-power dual-channel logic-level translator evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 voltages referenced to gnd. v cc , v l , ts ............................................................. -0.5v to +6v iovcc1, iovcc2 ................................... -0.5v to +(v cc + 0.5v) iovl1, iovl2 ............................................ -0.5v to +(v l + 0.5v) short-circuit duration iovcc1, iovcc2, iovl1, iovl2 to gnd ........................................... continuous v cc , iovcc_ maximum continuous current at +110 n c .... 100ma v l iovl_ maximum continuous current at +110 n c .......... 40ma ts maximum continuous current at +110 n c ..................... 70ma continuous power dissipation (t a = +70 n c) tdfn (derate 6.2mw/ n c above +70 n c) ...................... 496mw wlp (derate 11.8mw/ n c above +70 n c) ...................... 944mw operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (tdfn only, soldering, 10s) ............. +300 n c soldering temperature (reflow) ...................................... +260 n c tdfn junction-to-ambient thermal resistance ( b ja ) ........ 162 n c/w junction-to-case thermal resistance ( b jc ) ............... 20 n c/w wlp junction-to-ambient thermal resistance ( b ja ) .......... 85 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v cc = +1.65v to +5.5v, v l = +0.9v to min(v cc + 0.3v, +3.6v), t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3v, v l = +1.2v, and t a = +25 n c.) (notes 2, 3) package thermal characteristics (note 1) parameter symbol conditions min typ max units power supply power supply range v l 0.9 5.5 v v cc 1.65 5.5 v cc supply current i cc iovcc_ = v cc , iovl_ = v l , ts = v cc 7 15 f a v l supply current i l iovcc_ = v cc , iovl_ = v l , ts = v cc 3 6 f a v cc shutdown supply current i cc-shdn ts = gnd 0.4 1 f a ts = v cc , v l = gnd, iovcc_ = unconnected 0.4 1 v l shutdown supply current i l-shdn ts = gnd 0.1 1 f a ts = v l , v cc = gnd, iovl_ = unconnected 0.1 1 iovcc_, iovl_ three-state leakage current i leak t a = +25 n c, ts = gnd 0.1 1 f a ts input leakage current i leak_ts t a = +25 n c 1 f a v cc shutdown threshold v th_vcc ts = v l , v cc falling 0.8 1.35 v v l shutdown threshold v th_vl ts = v cc , v l falling, v l = 0.9v 0.25 0.6 0.86 v v l above v cc shutdown threshold v th_vl-vcc v l rising above v cc , v cc = +1.65v 0.4 0.73 1.1 v iovl_ pullup resistor r vl_pu inferred from v ohl measurements 3 7.6 12 k i iovcc_ pullup resistor r vcc_pu inferred from v ohc measurements 3 7.6 12 k i iovl_ to iovcc_ dc resistance r iovl-iovcc inferred from v olx measurements 6 17 i max14595 low-power dual-channel logic-level translator maxim integrated
3 electrical characteristics (continued) (v cc = +1.65v to +5.5v, v l = +0.9v to min(v cc + 0.3v, +3.6v), t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3v, v l = +1.2v, and t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units logic levels iovl_ input-voltage high v ihl iovl_ rising, v l = +0.9v, v cc = +1.65v (note 4) v l - 0.2 v iovl_ input-voltage low v ill iovl_ falling, v l = +0.9v, v cc = +1.65v (note 4) 0.15 v iovcc_ input-voltage high v ihc iovcc_ rising, v l = +0.9v, v cc = +1.65v (note 4) v cc - 0.4 v iovcc_ input-voltage low v ilc iovcc_ falling, v l = +0.9v, v cc = +1.65v (note 4) 0.2 v ts input-voltage high v ih ts rising, v l = +0.9v or +3.6v, v cc > v l v l - 0.15 v ts input-voltage low v il ts falling, v l = +0.9v or +3.6v, v cc > v l 0.2 v iovl_ output-voltage high v ohl iovl_ source current 20 f a, v iovcc_ = v l to v cc (v cc r v l ) 0.7 x v l v iovl_ output-voltage low v oll iovl_ sink current 5ma, v iovcc_ p 0.05v 0.2 v iovcc_ output-voltage high v ohc iovcc_ source current 20 f a, v iovl_ = v l 0.7 x v cc v iovcc_ output-voltage low v olc iovcc_ sink current 5ma, v iovl_ p 0.05v 0.25 v rise/fall time accelerator stage accelerator pulse duration v l = +0.9v, v cc = +1.65v 9 22 48 ns iovl_ output accelerator source impedance v l = +0.9v, iovl_ = gnd, v cc = +1.65v 26 i v l = +3.3v, iovl_ = gnd, v cc = +5v 6.8 iovcc_ output accelerator source impedance v cc = +1.65v, iovcc_ = gnd 26 i v cc = +5v, iovcc_ = gnd 6.5 thermal protection thermal shutdown t shdn +150 n c thermal hysteresis t hyst 10 n c max14595 low-power dual-channel logic-level translator maxim integrated
4 timing characteristics (v cc = +1.65v to +5.5v, v l = +0.9v to +3.6v, v cc r v l , ts = v l , c vcc = 1 f f, c vl = 0.1 f f, c iovl_ p 100pf, c iovcc_ p 100pf, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3v, v l = +1.2v and t a = +25 n c. all timing is 10% to 90% for rise time and 90% to 10% for fall time.) (note 5) note 2: all devices are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and not production tested. note 3: v l must be less than or equal to v cc during normal operation. however, v l can be greater than v cc during startup and shutdown conditions. note 4: v ihl , v ill , v ihc , and v ilc are intended to define the range where the accelerator triggers. note 5: guaranteed by design. note 6: external pullup resistors are required. parameter symbol conditions min typ max units turn-on time for q1 t on v ts = 0v to v l (see the block diagram ) 160 400 f s iovcc_ rise time t rcc push-pull driving, v l = +1.2v, v cc = +3v (figure 1) 8 22 ns open-drain driving, v l = +1.2v, v cc = +3v (figure 2) 11 iovcc_ fall time t fcc push-pull driving, v l = +1.2v, v cc = +3v (figure 1) 5 15 ns open-drain driving, v l = +1.2v, v cc = +3v (figure 2) 6 iovl_ rise time t rl push-pull driving, v l = +1.2v, v cc = +3v (figure 3) 4 13 ns open-drain driving, v l = +1.2v, v cc = +3v (figure 4) 16 iovl_ fall time t fl push-pull driving, v l = +1.2v, v cc = +3v (figure 3) 2.8 12 ns open-drain driving, v l = +1.2v, v cc = +3v (figure 4) 3.3 propagation delay (driving iovl_) t pd_lcc push-pull driving, v l = +1.2v, v cc = +3v (figure 1) rising 7.6 19 ns falling 3 9 propagation delay (driving iovcc_) t pd_ccl push-pull driving, v l = +1.2v, v cc = +3v (figure 3) rising 3 5 ns falling 1.5 7 channel-to-channel skew t skew input rise time/fall time < 6ns 1.5 ns maximum data rate push-pull operation 8 mhz open-drain operation (note 6) 4 max14595 low-power dual-channel logic-level translator maxim integrated
5 figure 1. push-pull driving iovl_ figure 2. open-drain driving iovl_ figure 3. push-pull driving iovcc_ figure 4. open-drain driving iovcc_ iovl_ v l c l 20pf r s 50i v l v cc v cc iovcc_ gnd ts 50 % 90 % 90 % 10 % 10 % 50 % 50 % 50 % t rcc t fc c t pd_lcc t pd_lcc max14595 iovl_ v l c l 20pf 1ki 1ki v l v cc v cc iovcc_ gnd ts 90 %9 0% 10 % 10 % 50 % t rcc t fc c t pd_lcc t pd_lcc r dson 5i 50 % max14595 iovl_ v l c l 20pf v l v cc v cc iovcc_ gnd ts 50 % 50 % 50 % 90 % 10 % 10 % 50 % t rl t pd_ccl t pd_ccl r s 50i t fl 90 % max14595 iovl_ v l c l 20pf 1ki 1ki v l v cc v cc iovcc_ gnd ts 90 % 10 % 10 % 50 % t pd_ccl t rl t fl t pd_ccl r dson 5i 90 % 50 % max14595 max14595 low-power dual-channel logic-level translator maxim integrated
6 typical operating characteristics (v cc = +3v, v l = +1.5v, r l = 1m i , c l = 15pf, push-pull driving data rate = 8mbps, t a = +25 n c, unless otherwise noted.) v l dynamic supply current vs. v cc supply voltage (open-drain driving one iovl_) max14595 toc01 v cc (v) v l supply current (a) 4.95 4.40 3.30 3.85 2.75 2.20 20 40 60 80 100 120 140 160 180 200 0 1.65 5.50 v l dynamic supply current vs. v cc supply voltage (push-pull driving one iovcc_) max14595 toc02 v cc (v) v l supply current (a) 4.95 4.40 3.30 3.85 2.75 2.20 20 40 60 80 100 120 140 160 180 200 0 1.65 5.50 v cc dynamic supply current vs. v l supply voltage (push-pull driving one iovl_) max14595 toc03 v l (v) v cc supply current (a) 3.3 3.0 1.2 1.5 1.8 2.4 2.1 2.7 100 200 300 400 500 600 700 800 0 0.9 3.6 v cc dynamic supply current vs. v l supply voltage (open-drain driving one iovcc_) max14595 toc04 v l (v) v cc supply current (a) 3.3 3.0 1.2 1.5 1.8 2.4 2.1 2.7 100 200 300 400 500 600 700 800 0 0.9 3.6 v l dynamic supply current vs. temperature (open-drain driving one iovl_) max14595 toc05 temperature (c) v l supply current (a) 60 35 10 -15 20 40 60 80 100 120 140 160 180 200 0 -40 85 v l dynamic supply current vs. temperature (push-pull driving one iovcc_) max14595 toc06 temperature (c) v l supply current (a) 60 35 10 -15 20 40 60 80 100 120 140 160 180 200 0 -40 85 v l dynamic supply current vs. capacitive load (open-drain driving one iovl_) max14595 toc07 capacitive load (pf) v l supply current (a) 80 60 40 20 20 40 60 80 100 120 140 160 180 200 0 0 100 v cc dynamic supply current vs. capacitive load (push-pull driving one iovl_) max14595 toc08 capacitive load (pf) v cc supply current (ma) 80 60 20 40 0.2 0.4 0.6 0.8 1.2 1.0 1.4 1.6 0 0 100 rise/fall time vs. capacitive load (push-pull driving one iovl_) max14595 toc09 capacitive load (pf) rise/fall time (ns) 80 60 40 20 5 10 15 20 25 30 35 0 0 100 r s = 50 t fcc t rcc max14595 low-power dual-channel logic-level translator maxim integrated
7 typical operating characteristics (continued) (v cc = +3v, v l = +1.5v, r l = 1m i , c l = 15pf, push-pull driving data rate = 8mbps, t a = +25 n c, unless otherwise noted.) propagation delay vs. capacitive load (push-pull driving one iovl_) max14595 toc10 capacitive load (pf) propagation delay (ns) 80 60 20 40 2 4 6 8 12 10 14 16 0 0 100 r s = 50 t pd_lcc_rise t pd_lcc_fall rise/fall time vs. capacitive load (push-pull driving one iovcc_) max14595 toc11 capacitive load (pf) rise/fall time (ns) 80 60 20 40 2 4 6 8 12 10 14 16 0 0 100 r s = 50 t fl t rl propagation delay vs. capacitive load (push-pull driving one iovcc_) max14595 toc12 capacitive load (pf) propagation delay (ns) 80 60 20 40 1 2 3 4 6 5 7 8 0 0 100 r s = 50 t pd_ccl_fall t pd_ccl_rise r iovl-iovcc vs. v l max14595 toc13 v l (v) r iovl-iovcc () 5 4 3 2 1 1 2 3 4 5 6 7 8 9 0 06 v cc = 1.65v v cc = 3.3v v cc = 5.5v v iovl_ = 0.05v i iovcc_ = 3.3ma rail-to-rail driving (push-pull driving one iovl_) (v l = +1.5v, v cc = +3.3v, c l = 15pf, r l = 1m , r s = 50 ) max14595 toc14 40ns/div iovl_ 1v/div iovcc_ 1v/div rail-to-rail driving (open-drain driving one iovl_) (v l = +1.5v, v cc = +3.3v, c l = 100pf, r l = 50 , r s = 50 , pullup on iovl_/iovcc_ = 1k ) max14595 toc15 40ns/div iovl_ 1v/div iovcc_ 1v/div exiting shutdown mode (v l = 1.2v, v cc = 3.0v, iovcc_ = 0v, c l = 100pf, r pu_vl = 50 ) max14595 toc16 40s/div ts 500mv/div iovl_ 500mv/div max14595 low-power dual-channel logic-level translator maxim integrated
8 pin description pin configurations bump/pin name function wlp tdfn a1 1 v l logic supply voltage, +0.9v to min(v cc + 0.3v, +3.6v). bypass v l to gnd with a 0.1 f f ceramic capacitor as close as possible to the device. a2 2 iovl2 input/output 2. reference to v l . a3 3 iovl1 input/output 1. reference to v l . a4 4 ts active low three-state input. drive ts low to place the device in shutdown mode with high-impedance output and internal pullup resistors disconnected. drive ts high for normal operation. b1 8 v cc power-supply voltage, +1.65v to +5.5v. bypass v cc to gnd with a 1 f f ceramic capacitor as close as possible to the device. b2 7 iovcc2 input/output 2. reference to v cc . b3 6 iovcc1 input/output 1. reference to v cc . b4 5 gnd ground 13 4 86 5 2 7 v cc v cc iovcc1 iovcc1 gnd gnd max14595 iovcc2 iovcc2 v l v l iovl1 iovl1 iovl2 iovl2 tdfn bumps on bottom ts ts + a 12 3 4 b + top view max14595 wlp max14595 low-power dual-channel logic-level translator maxim integrated
9 block diagram detailed description the max14595 is a dual-channel, bidirectional level trans - lator. the device translates low voltage down to +0.9v on the v l side to high voltage on the v cc side and vice-ver - sa. the device is optimized for open-drain and high-speed operation, such as i 2 c bus and mdio bus. the device has low on-resistance (17 i max), which is important for high-speed, open-drain operation. the device also features internal pullup resistors that are active when the corresponding power is on and ts is high. level translation for proper operation, ensure that +1.65v p v cc p +5.5v, and +0.9v p v l p v cc . when power is supplied to v l while v cc is less than v l , the device automatically disables logic-level translation function. also, the device enters shutdown mode when ts = gnd. high-speed operation the device meets the requirements of high-speed i 2 c and mdio open-drain operation. the maximum data rate is at least 4mhz for open-drain operation with the total bus capacitance equal to or less than 100pf. three-state input ts the device features a three-state input that can put the device into high-impedance mode. when ts is low, iovcc_ and iovl_ are all high impedance and the inter - nal pullup resistors are disconnected. when ts is high, the internal pullup resistors are connected when the corresponding power is in regulation, and the resistors are disconnected at the side that has no power on. in many portable applications, one supply is turned off but the other side is still operating and requires the pullup resistors to be present. this feature eliminates the need for external pullup resistors. the level translation function is off until both power supplies are in range. thermal-shutdown protection the device features thermal-shutdown protection to protect the part from overheating. the device enters thermal shutdown when the junction temperature exceeds +150 n c (typ), and the device is back to normal operation again after the temperature drops by approximately 10 n c (typ). when the device is in thermal shutdown, the level translator is disabled. one-shoot block one-shoot block en control block gate drive iovl_ nq 1 iovcc_ v l v cc ts max14595 max14595 low-power dual-channel logic-level translator maxim integrated
10 ordering information note: all devices are specified over -40c to +85c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated .com/pa ckages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part top mark pin-package max14595eta+t bnt 8 tdfn max14595ewa+t aae 8 wlp package type package code outline no. land pattern no. 8 tdfn t822cn+1 21-0487 90-0349 8 wlp w80a1+1 21-0555 refer to application note 1891 max14595 low-power dual-channel logic-level translator maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 11 ? 2011 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/11 initial release max14595 low-power dual-channel logic-level translator

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